The present invention is related to a protective circuit for avoiding electrostatic discharge (ESD) damage. The ESD protective circuit is built in a driving matrix thin film transistor (TFT) liquid crystal display.
FIG. 2 shows a conventional driving matrix liquid crystal display 10 utilizing thin film transistor switch cells (TFTs). The liquid crystal display 10 includes multiple TFTs 2 arranged into a matrix and pixel capacitors 1 connected with the drains of the TFTs 2. The pixel capacitor 1 includes a liquid crystal capacitor 1a formed of a liquid crystal layer between pixel electrode and Vcom and a storage capacitor 1b parallel to the liquid crystal capacitor 1a. The other ends of the liquid crystal capacitor 1a and the storage capacitor 1b are electrically connected to an equal potential contact 4 disposed on a corresponding substrate. A scanning signal line 3 is electrically connected to the gate of the TFTs 2. The data signal line 5 is electrically connected to the source of the TFTs 2. The scan signal provided via the scanning signal line 3 makes the TFTs 2 in an on/off state. When the TFTs 2 is turned on, image signal voltage via the data signal line 5 is provided for the source of the TFTs 2 to charge the pixel capacitor to a voltage level corresponding to the source. The scan line and data line pads adapted to the driving chip are denoted by 8 and 9.
The TFT ESD protective circuit 7 is disposed between the scanning signal line 3 and the Vcom 6 (common electrode) and between the data signal line 5 and the Vcom 6. When electrostatic voltage is generated, the TFT ESD protective circuit 7 serves to eliminate the electrostatic voltage to protect the TFTs 2 from being damaged by electrostatic voltage. In manufacturing procedure of the liquid crystal display, the electrostatic voltage is generated easily when assembling the driving matrix substrate (on which switch cells are disposed), especially when arranging the ICs for driving the LCD on the driving matrix substrate.
FIG. 3 shows a conventional TFT ESD protective circuit 11. The TFT ESD protective circuit 11 includes two TFT diodes t1, t2 reversely connected. The pattern of the TFT ESD protective circuit symbol is as shown in FIG. 4. The gate electrode G and drain electrode D of the TFT t1 are short-circuited and connected to the scanning signal line 3 and the data signal line 5. The source electrode S of the TFT t1 is connected to the Vcom 6. The source electrode S of the TFT t2 is connected to the scanning signal line 3 and data signal line 5. The gate electrode G and drain electrode D of the TFT t2 are short-circuited and connected to the Vcom 6.
The TFT t1 of the TFT ESD protective circuit 11 is an element for discharging positive electrostatic voltage, while the TFT t2 of the TFT ESD protective circuit 11 is an element for discharging negative electrostatic voltage. When positive electrostatic voltage is generated, the electrostatic voltage level rises higher than the threshold voltage of TFT. At this time, the transistor t1 is turned on and the positive electrostatic voltage via the scanning signal line 3 and data signal line 5 is discharged by the transistor t1. Similarly, when negative electrostatic voltage is generated, the transistor t2 discharges the negative electrostatic voltage to achieve ESD protection effect.
When the above TFT ESD protective circuit 11 protects the internal TFT array, the TFT ESD protective circuit 11 itself is in the danger of being damaged by the electrostatic voltage. In the case that the TFT cell is damaged by the electrostatic voltage, the insulating layer of the gate electrode will be broken down by the electrostatic voltage to cause very great leaking current. For example, in the case that the insulating layer of the gate electrode of the TFT t1 is broken down, the knot of gate electrode at the TFT t1 and the source electrode will be short-circuited. This leads to short-circuit of the scanning signal line 3, data signal line 5 and Vcom 6. This will form a defect on the display panel. The defect will result in that the picture cannot be normally shown in the cell test and module driving of the manufacturing procedure. This problem will affect the yield of products. Therefore, it is tried by the applicant to solve the above problem.